Table of Contents
Advertisement
Reset and clock control (RCC)
7.4.34
RCC CPU2 AHB2 peripheral clock enable register
(RCC_C2AHB2ENR)
Address offset: 0x14C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: CPU2 IO port H clock enable
This bit is set and cleared by software.
0: IO port H clock disabled for CPU2
1: IO port H clock enabled for CPU2
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCEN: CPU2 IO port C clock enable
This bit is set and cleared by software.
0: IO port C clock disabled for CPU2
1: IO port C clock enabled for CPU2
Bit 1 GPIOBEN: CPU2 IO port B clock enable
This bit is set and cleared by software.
0: IO port B clock disabled for CPU2
1: IO port B clock enabled for CPU2
Bit 0 GPIOAEN: CPU2 IO port A clock enable
This bit is set and cleared by software.
0: IO port A clock disabled for CPU2
1: IO port A clock enabled for CPU2
342/1454
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
GPIOH
Res.
Res.
EN
rw
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
GPIOC
Res.
Res.
Res.
EN
rw
RM0453
17
16
Res.
Res.
1
0
GPIOB
GPIOA
EN
EN
rw
rw
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL55JC and is the answer not in the manual?