Figure 151. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32WL55JC Reference Manual

RM0453
Counter clock = CK_CNT = CK_PSC
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 154
TIM1_AF1[17:14] and
TIM1_OR1[1:0]
ETR pin
(1)
1. Refer to Figure 150: TIM1 ETR input
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
Figure 153. Control circuit in external clock mode 1
TI2
CNT_EN
Counter register
TIF
gives an overview of the external trigger input block.
Figure 154. External trigger input block
ETR
0
Divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR
circuitry.
34
Write TIF=0
or
ETRP
Filter
f downcounter
DTS
ETF[3:0]
(internal clock)
TIMx_SMCR
RM0453 Rev 2
Advanced-control timer (TIM1)
35
TI2F or
TI1F or
Encoder
mode
TRGI
External clock
mode 1
ETRF External clock
mode 2
Internal clock
CK_INT
mode
ECE SMS[2:0]
TIMx_SMCR
36
MS31087V2
CK_PSC
MSv47461V1
743/1454
822