ST STM32WL55JC Reference Manual page 259

RM0453
Bit 9 VBRS: V
Bit 8 VBE: V
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 WP3: Wakeup pin WKUP3 polarity
Bit 1 WP2: Wakeup pin WKUP2 polarity
Bit 0 WP1: Wakeup pin WKUP1 polarity
6.6.5 PWR status register 1 ( PWR_SR1 )
This register is not reset when exiting Standby modes.
Access: two additional APB cycles are needed to read this register versus a standard APB
read.
Address offset: 0x010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
WUFI C2HF Res. Res.
r r
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Internal wakeup interrupt flag
Bit 14 C2HF: CPU2 hold interrupt flag
Bits 13:12 Reserved, must be kept at reset value.
battery charging resistor selection
BAT
0: V charging through a 5 kΩ resistor
BAT
1: V charging through a 1.5 kΩ resistor
BAT
battery charging enable
BAT
0: V battery charging disabled
BAT
1: V battery charging enabled
BAT
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res.
r
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all
internal wakeup sources are cleared.
This bit is set when a CPU2 wakeup is detected (except an illegal access wakeup) when
C2BOOT = 0. It is cleared by PWR_SCR.CC2HF.
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
r
RM0453 Rev 2
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. WUF3
r
17 16
Res. Res.
1 0
WUF2 WUF1
r r
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