ST STM32WL55JC Reference Manual page 328

Reset and clock control (RCC)
Bit 22 I2C2SMEN: I2C2 clock enable during CPU1 CSleep and CStop modes
Bit 21 I2C1SMEN: I2C1 clock enable during CPU1 CSleep and CStop modes
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2SMEN: USART2 clock enable during CPU1 CSleep and CStop modes
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2SMEN: SPI2S2 clock enable during CPU1 CSleep and CStop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during CPU1 CSleep and CStop modes
Bit 10 RTCAPBSMEN: RTC APB bus clock enable during CPU1 CSleep and CStop modes
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2SMEN: Timer 2 clock enable during CPU1 CSleep and CStop modes
328/1454
This bit is set and cleared by software.
0: I2C2 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: I2C2 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
This bit is set and cleared by software.
0: I2C1 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: I2C1 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
This bit is set and cleared by software.
0: USART2 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: USART2 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled
during CPU1 CStop mode
This bit is set and cleared by software.
0: SPI2S2 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: SPI2S2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
This bit is set and cleared by software.It is forced to 1 by hardware when the hardware
WWDG_SW option is reset.
0: Window watchdog clock disabled by the clock gating during CPU1 CSleep and CStop
modes
1: Window watchdog clocks enabled by the clock gating during CPU1 CSleep mode,
disabled during CPU1 CStop mode
This bit is set and cleared by software. RTC kernel clock is controlled by the RTCEN bit in
the RCC_BDCR register.
0: RTC APB bus clock disabled during by the clock gating during CPU1 CSleep and CStop
modes
1: RTC APB bus clock enabled during by the clock gating during CPU1 CSleep mode,
disabled during CPU1 CStop mode
This bit is set and cleared by software.
0: TIM2 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: TIM2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1
CStop mode
RM0453 Rev 2
RM0453