Table 89. Cpu1 Vector Table; Figure 53. Interrupt Block Diagram - ST STM32WL55JC Reference Manual

RM0453
Type of
priority
27 34 Settable
28 35 Settable
29 36 Settable
30 37 Settable
31 38 Settable
32 39 Settable
33 40 Settable
34 41 Settable
35 42 Settable
36 43 Settable
37 44 Settable
38 45 Settable
39 46 Settable
40 47 Settable
41 48 Settable EXTI[15:10]
42 49 Settable RTC_ALARM
43 50 Settable
44 51 Settable
45 52 Settable IPCC_C1_RX_IT
46 53 Settable IPCC_C1_TX_IT
47 54 Settable
48 55 Settable
49 56 Settable
50 57 Settable
51 58 Settable
52 59 Settable
53 60 Settable
54 61 Settable DMA2_CH1
55 62 Settable DMA2_CH2
56 63 Settable DMA2_CH3
57 64 Settable DMA2_CH4
58 65 Settable DMA2_CH5
Table 89. CPU1 vector table (continued)
Acronym
TIM2 Timer 2 global interrupt
TIM16 Timer 16 global interrupt
TIM17 Timer 17 global interrupt
I2C1_EV I2C1 event interrupt
I2C1_ER I2C1 error interrupt
I2C2_EV I2C2 event interrupt
I2C2_ER I2C2 error interrupt
SPI1 SPI1 global interrupt
SPI2S2 SPI2S2 global interrupt
USART1 USART1 global interrupt
USART2 USART2 global interrupt
LPUART1 LPUART1 global interrupt
LPTIM1 LP timer 1 global interrupt
LPTIM2 LP timer 2 global interrupt
EXTI line [15:10] interrupt through EXTI[15:10]
(IMR1[31:26])
RTC alarms A and B interrupt
LPTIM3 LP timer 3 global interrupt
Reserved Reserved
IPCC CPU1 RX occupied interrupt
IPCC CPU1 TX free interrupt
HSEM Semaphore interrupt 0 to CPU1
I2C3_EV I2C3 event interrupt
I2C3_ER I2C3 error interrupt
Radio IRQ, Radio IRQs
Busy RFBUSY interrupt through EXTI[45]
AES AES global interrupt
True RNG True random number generator interrupt
PKA Private key accelerator interrupt
DMA2 channel 1 non-secure interrupt
DMA2 channel 2 non-secure interrupt
DMA2 channel 3 non-secure interrupt
DMA2 channel 4 non-secure interrupt
DMA2 channel 5 non-secure interrupt
Nested vectored interrupt controller (NVIC)
Description
RM0453 Rev 2
(1)(2)
Address
0x0000 00AC
0x0000 00B0
0x0000 00B4
0x0000 00B8
0x0000 00BC
0x0000 00C0
0x0000 00C4
0x0000 00C8
0x0000 00CC
0x0000 00D0
0x0000 00D4
0x0000 00D8
0x0000 00DC
0x0000 00E0
0x0000 00E4
0x0000 00E8
0x0000 00EC
0x0000 00F0
0x0000 00F4
0x0000 00F8
0x0000 00FC
0x0000 0100
0x0000 0104
0x0000 0108
0x0000 010C
0x0000 0110
0x0000 0114
0x0000 0118
0x0000 011C
0x0000 0120
0x0000 0124
0x0000 0128
501/1454
504