ST STM32WL55JC Reference Manual page 444

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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System configuration controller (SYSCFG)
Table 75. SYSCFG register map and reset values (continued)
Offset
Register
SYSCFG_IMR1
0x100
Reset value
SYSCFG_IMR2
0x104
Reset value
SYSCFG_C2IMR1
0x108
Reset value
SYSCFG_C2IMR2
0x10C
Reset value
0x110 to
Reserved
0x204
SYSCFG_RFDCR
0x208
Reset value
Refer to
444/1454
0
0 0
0 0
0 0
0 0
0
0 0
0 0
0 0
0 0
Section 2.6
for the register boundary addresses.
0
0
0
0
0
0 0
0 0
0 0
0
0
0 0
Reserved
RM0453 Rev 2
0 0
0 0
0
0
0
0 0
0 0
0
0
0
0 0
RM0453
0
0
0 0
0 0
0 0
0 0
0

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