Gtzc Tzsc Unprivileged Watermark 3 Register (Gtzc_Tzsc_Mpcwm3_Upwmr) - ST STM32WL55JC Reference Manual

Global security controller (GTZC)
3.6 GTZC TZIC registers
All GTZC TZIC registers are accessed by words (32-bit), halfwords (16-bit) and bytes (8-bit).
3.6.1 GTZC TZIC interrupt enable register 1 (GTZC_TZIC_IER1)
Address offset: 0x000
Reset value: 0xFFFF FFFF
when security is enabled (ESE = 1)
Reset value: 0x0000 0000
when security is disabled (ESE = 0)
This register can only be access by a secure privileged access for read and write.
A non-secure or unprivileged access is ignored and return zero data, and an illegal access
event is generated.
Note: When the system is non-secure (ESE = 0), this register cannot be written and is read zero.
No illegal access interrupt is generated.
31 30 29
Res. Res. Res. Res.
15 14 13
SRAM2
Res. Res. PKAIE
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKAIE: Illegal access event interrupt enable bit for PKA
Bit 12 SRAM2IE: Illegal access event interrupt enable bit for SRAM2
Bit 11 SRAM1IE: Illegal access event interrupt enable bit for SRAM1
Bit 10 FLASHIE: Illegal access event interrupt enable bit for Flash memory
Bit 9 DMAMUX1IE: Illegal access event interrupt enable bit for DMAMUX1
Bit 8 DMA2IE: Illegal access event interrupt enable bit for DMA2
92/1454
28 27 26 25
Res. Res. Res.
12 11 10 9
SRAM1 FLASH DMAM
IE IE IE UX1IE
rw rw rw rw
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
24 23 22
Res. Res. Res.
8 7 6
DMA2 DMA1 FLASH
PWRIE
IE IE IFIE
rw rw rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SUBG
HZSP RNGIE AESIE
IIE
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
TZSC
TZICIE
IE
rw rw