ST STM32WL55JC Reference Manual page 360

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Reset and clock control (RCC)
Off-
Register
set
RCC_
APB3SMENR
0x084
Reset value
RCC_CCIPR
0x088
0 0 0 0
Reset value
0x08C
Reserved
RCC_BDCR
0x090
Reset value
RCC_CSR
0x094
0 0 0 0 1 1 0 0 0
Reset value
0x098
to
Reserved
0x104
RCC_
EXTCFGR
0x108
Reset value
0x10C
to
Reserved
0x144
360/1454
Table 63. RCC register map and reset values (continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
Reserved
0 0
0 1
Reserved
1 1
Reserved
RM0453 Rev 2
0 0 0 0
0
0 0 0 0 0 0 0 0 0 0
0 1 1 0
0
C2HPRE
SHDHPRE
[3:0]
0 0 0 0 0 0 0 0
RM0453
1
0 0
[3:0]

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