Figure 139. Counter Timing Diagram, Internal Clock Divided By 4; Figure 140. Counter Timing Diagram, Internal Clock Divided By N - ST STM32WL55JC Reference Manual

RM0453
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 142. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
Timerclock = CK_CNT
Update event (UEV)
Update interrupt flag (UIF)
1.
Here, center-aligned mode 1 is used (for more details refer to
CK_PSC
CEN
Counter register
Counter underflow
Counter overflow
04 03 02 01 00 01
Section 25.4: TIM1
RM0453 Rev 2
Advanced-control timer (TIM1)
02 03 04 05 06 05
registers).
04 03
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