ST STM32WL55JC Reference Manual page 354

Reset and clock control (RCC)
7.4.45 RCC CPU2 APB2 peripheral clock enable in Sleep mode register
(RCC_C2APB2SMENR)
Address offset: 0x180
Reset value: 0x0006 5A00
Access: word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART1 SPI1
Res. Res.
SMEN SMEN
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM17 timer clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: TIM17 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: TIM17 timer clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
Bit 17 TIM16SMEN: TIM16 timer clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: TIM16 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: TIM16 timer clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: USART1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: USART1 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: SPI1 clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: SPI1 clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2
CStop mode
Bit 11 TIM1SMEN: TIM1 timer clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: TIM1 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: TIM1 timer clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
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28 27 26 25
Res. Res. Res.
12 11 10 9
TIM1 ADC
Res.
SMEN SMEN
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 2
21 20 19 18
TIM17
Res. Res. Res.
SMEN
rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
TIM16
Res.
SMEN
rw
1 0
Res. Res.