Sleep Mode; Table 48. Cpu Wakeup Versus System Operating Mode - ST STM32WL55JC Reference Manual

RM0453
following alternative RTC clock sources can be selected by programming the RTCSEL[1:0]
bits in the
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
•
Low-power internal RC oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC alarm event, it is necessary to:
•
Configure the EXTI line 18 to be sensitive to rising edge.
•
Configure the RTC to generate the RTC alarm.
To wakeup from Standby mode, there is no need to configure the EXTI line 18.
To wakeup from Stop mode with an RTC wakeup event, it is necessary to:
•
Configure the EXTI line 20 to be sensitive to rising edge.
•
Configure the RTC to generate the RTC alarm.
To wakeup from Standby mode, there is no need to configure the EXTI line 20.
6.6 PWR registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
6.6.1 PWR control register 1 (PWR_CR1)
This register is reset after wakeup from Standby mode, except for bit field LPMS[2:0].
Access: additional APB cycles are used to access this register versus those used for a
standard APB access (three for a write and two for a read).
Address offset: 0x000
Reset value: 0x0000 0200
31 30 29
Res. Res. Res. Res.
15 14 13
Res. LPR Res. Res.
rw
RCC Backup domain control register
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. VOS[1:0]
rw rw
(RCC_BDCR):
24 23 22
Res. Res. Res.
8 7 6
DBP Res. Res. FPDS
rw
RM0453 Rev 2
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FPDR
rw rw rw rw
17 16
Res. Res.
1 0
LPMS[2:0]
rw rw
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