Gtzc Tzic Registers; Gtzc Tzic Interrupt Enable Register 1 (Gtzc_Tzic_Ier1) - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Global security controller (GTZC)
Bit 13 PKAMF: Illegal access event interrupt status flag before masking for PKA
Bit 12 SRAM2MF: Illegal access event interrupt status flag before masking for SRAM2
Bit 11 SRAM1MF: Illegal access event interrupt status flag before masking for SRAM1
Bit 10 FLASHMF: Illegal access event interrupt status flag before masking for Flash memory
Bit 9 DMAMUX1MF: Illegal access event interrupt status flag before masking for DMAMUX1
Bit 8 DMA2MF: Illegal access event interrupt status flag before masking for DMA2
Bit 7 DMA1MF: Illegal access event interrupt status flag before masking for DMA1
Bit 6 FLASHIFMF: Illegal access event interrupt status flag before masking for Flash interface
Bit 5 PWRMF: Illegal access event interrupt status flag before masking for PWR
Bit 4 SUBGHZSPIMF: Illegal access event interrupt status flag before masking for sub-GHz SPI
Bit 3 RNGMF: Illegal access event interrupt status flag before masking for RNG
Bit 2 AESMF: Illegal access event interrupt status flag before masking for AES
Bit 1 TZSCMF: Illegal access event interrupt status flag before masking for GTZC TZSC
Bit 0 TZICMF: Illegal access event interrupt status flag before masking for GTZC TZIC
94/1454
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending.
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
0: No illegal access event interrupt pending
1: Illegal access event interrupt pending
RM0453 Rev 2
RM0453

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