Table 110. Adc Register Map And Reset Values - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Analog-to-digital converter (ADC)
Table 110. ADC register map and reset values (continued)
Offset
Register
ADC_IER
0x04
Reset value
ADC_CR
0x08
Reset value
0
ADC_CFGR1
0x0C
Reset value
ADC_CFGR2
0x10
Reset value
0
ADC_SMPR
0x14
Reset value
0x18
Reserved
0x1C
Reserved
ADC_AWD1TR
0x20
Reset value
ADC_AWD2TR
0x24
Reset value
ADC_CHSELR
(CHSELRMOD=
0x28
0)
Reset value
ADC_CHSELR
(CHSELRMOD=
0x28
1)
Reset value
0
ADC_AWD3TR
0x2C
Reset value
0x30
0x34
Reserved
0x38
0x3C
ADC_DR
0x40
Reset value
...
Reserved
0xA0
ADC_AWD2CR
Reset value
590/1454
0
AWDCH[4:0]
0
0
0
0
0
0
0
0
0
0
0
HT1[11:0]
1
1
1
1
1
HT2[11:0]
1
1
1
1
1
SQ8[3:0]
SQ7[3:0]
SQ6[3:0]
0
0
0
0
0
0
0
0
HT3[11:0]
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
SQ5[3:0]
SQ4[3:0]
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Reserved
0
0
Reserved
0
0
0
0
RM0453 Rev 2
0
0
0
0
0
EXTSEL
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
SMP2
[2:0]
0
0
0
0
0
0
0
0
LT1[11:0]
0
0
0
0
0
0
0
LT2[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SQ3[3:0]
SQ2[3:0]
0
0
0
0
0
0
0
0
0
LT3[11:0]
0
0
0
0
0
0
0
DATA[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0453
0
0
0
0
0
0
0
0
0
RES
[1:0]
0
0
0
0
0
0
0
0
0
0
SMP1
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SQ1[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

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