Table 46. Mcu And Sub-Ghz Radio Operating Modes - ST STM32WL55JC Reference Manual

RM0453
exiting the Stop 2 mode, the MCU is in Run mode (range 1 or range 2 depending on VOS bit
in PWR_CR1).
Stop 2
Mode entry
Mode exit
Wakeup latency
6.5.10 Standby mode
The Standby mode allows the lowest power consumption to be achieved with BOR. It is
based on the CPU Deep-Sleep mode, with the voltage regulators disabled (except when
SRAM2 content is preserved). PLL, HSI16, MSI and HSE32 oscillators are also switched
off.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry (see
the PWR control register 3
provides the supply to SRAM2 only. When the SRAM2 retention is enabled the device only
enters Standby mode once the low-power regulator is ready. The REGLPS bit can be used
to check that the low-power regulator is ready. Immediately exiting from Standby mode with
SRAM2 retention may be delayed until the low-power regulator is ready.
BOR is always available in Standby modes. The consumption is increased when thresholds
higher than V
BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows the current consumption
to be decreased in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector results in a non-generation of PDR reset.
Table 53. Stop 2 mode
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b010 in PWR_CR1 and/or PWR_C2CR1 or higher
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b010 in PWR_CR1 and/or PWR_C2CR1 or higher
Note: To enter Stop 2 mode, all EXTI line pending bits in
(EXTI_PR1), and
flags generating wakeup interrupts must be cleared. Otherwise, the
Standby mode entry procedure is ignored and program execution
continues.
Any EXTI line configured in Interrupt mode or event mode (regardless if the
corresponding EXTI interrupt vector is enabled in the NVIC). The interrupt source
can be external interrupts or peripherals with wakeup capability. Refer to
CPU1 vector table, and
Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup
time from Low-power mode + Flash wakeup time from Stop 2 mode.
Figure 18). SRAM2 content can be preserved if the bit RRS is set in
(PWR_CR3). In this case the low-power regulator is enabled and
are used.
BOR0
RM0453 Rev 2
Description
EXTI pending register (EXTI_PR2)), and the peripheral
Table 90: CPU2 vector table.
Power control (PWR)
EXTI pending register
Table 89:
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