ST STM32WL55JC Reference Manual page 981

RM0453
30.4.4 IWDG status register (IWDG_SR)
Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 WVU: Watchdog counter window value update
Bit 1 RVU: Watchdog counter reload value update
Bit 0 PVU: Watchdog prescaler value update
Note: If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set by hardware to indicate that an update of the window value is ongoing. It is
reset by hardware when the reload value update operation is completed in the V
domain (takes up to five cycles).
Window value can be updated only when WVU bit is reset.
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the V
(takes up to five cycles).
Reload value can be updated only when RVU bit is reset.
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the V
domain (takes up to five cycles).
Prescaler value can be updated only when PVU bit is reset.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 2
Independent watchdog (IWDG)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. WVU
r
DD
17 16
Res. Res.
1 0
RVU PVU
r r
voltage
DD
voltage domain
voltage
DD
981/1454
983