ST STM32WL55JC Reference Manual page 13

RM0453
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
10.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
10.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
10.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
10.3.13 Using the LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . . . . . . . 400
10.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 400
10.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
10.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
10.4.10 GPIOx alternate function high register (GPIOx_AFRH) (x = A to B) . . 407
10.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B) . . . . . . . . . . . . . . . 408
10.4.12 GPIOC mode register (GPIOC_MODER) . . . . . . . . . . . . . . . . . . . . . . 408
10.4.13 GPIOC output type register (GPIOC_OTYPER) . . . . . . . . . . . . . . . . . 409
10.4.14 GPIOC output speed register (GPIOC_OSPEEDR) . . . . . . . . . . . . . . 410
10.4.15 GPIOC pull-up/pull-down register (GPIOC_PUPDR) . . . . . . . . . . . . . 411
10.4.16 GPIOC input data register (GPIOC_IDR) . . . . . . . . . . . . . . . . . . . . . . 411
10.4.17 GPIOC output data register (GPIOC_ODR) . . . . . . . . . . . . . . . . . . . . 412
10.4.18 GPIOC bit set/reset register (GPIOC_BSRR) . . . . . . . . . . . . . . . . . . . 413
10.4.19 GPIOC configuration lock register (GPIOC_LCKR) . . . . . . . . . . . . . . . 414
10.4.20 GPIOC alternate function low register (GPIOC_AFRL) . . . . . . . . . . . . 415
10.4.21 GPIOC alternate function high register (GPIOC_AFRH) . . . . . . . . . . . 416
10.4.22 GPIOC bit reset register (GPIOC_BRR) . . . . . . . . . . . . . . . . . . . . . . . 416
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 395
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
GPIOx mode register (GPIOx_MODER) (x = A to B) . . . . . . . . . . . . . . 401
GPIOx output type register (GPIOx_OTYPER) (x = A to B) . . . . . . . . . 402
GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B) . . . . . . 402
GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) . . . . . 403
GPIOx input data register (GPIOx_IDR) (x = A to B) . . . . . . . . . . . . . . 404
GPIOx output data register (GPIOx_ODR) (x = A to B) . . . . . . . . . . . . 405
GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B) . . . . . . . . . . . 405
GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) . . . . . . 406
GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) . . . 407
RM0453 Rev 2
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