ST STM32WL55JC Reference Manual page 435

RM0453
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 SRAMBSY: SRAM1 or SRAM2 busy by erase operation
0: No SRAM1 or SRAM2 erase operation is ongoing.
1: SRAM1 or SRAM2 erase operation is ongoing.
See
Bit 0 SRAM2ER: SRAM2 erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at
the end of the SRAM2 erase operation.
Note: This bit is write-protected: setting this bit is possible only after the correct key sequence
11.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x01C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 SPF: SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software
by writing '1'.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ECCL: ECC lock
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the Flash ECC error connection to TIM1/16/17 break input.
0: ECC error disconnected from TIM1/16/17 break input.
1: ECC error connected to TIM1/16/17 break input.
Section 2.4: SRAM erase
is written in the SYSCFG_SKR register.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
System configuration controller (SYSCFG)
for more information on SRAM erase conditions
24 23 22
Res. Res. Res.
8 7 6
SPF Res. Res.
rc_w1
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. ECCL PVDL
rs rs
17 16
Res. Res.
1 0
SPL CLL
rs rs
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