Flash Program And Erase Operations - ST STM32WL55JC Reference Manual

Embedded Flash memory (FLASH)
change due to Flash operation requests by the other CPU, to limit the risk of receiving
a bus error when starting page erase).
3. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
4. Set PER and select the page to erase (PNB[6:0]) in FLASH_CR or FLASH_C2CR.
5. Set STRT in FLASH_CR or FLASH_C2CR.
6. Wait for BSY to be cleared in FLASH_SR or FLASH_C2SR.
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when the STRT bit is set,
and disabled automatically when the STRT bit is cleared, except if the HSI16 is previously
enabled with HSION in the RCC_CR register.
Flash mass erase
A user Flash memory mass erase requested by the CPU1 is only performed when the
system is non-secure (ESE = 0). When the system is secure (ESE = 1), a Flash memory
mass erase by the CPU1 is ignored and an illegal access event is generated.
When PCROP or WRP is enabled, any Flash memory mass erase is aborted and no erase
started.
Hide protection area and hide protection area disable provide no protection for mass erase.
PCROP
PCROP WRP
_RDP
No No
No Yes
0
Yes No
Yes Yes
No No
1
No Yes
Yes No
Yes Yes
1. When MER requested by the non-secure CPU1.
2. When requested by a secure bus master. When requested by a non-secure bus master, no WRPERR is generated and an
illegal access event is generated instead.
To perform a mass erase, follow the steps detailed below:
1. Check that no Flash memory operation is ongoing by checking BSY in FLASH_SR or
FLASH_C2SR.
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Table 14. Mass erase overview
Comment
Memory is erased
Erase aborted (no erase started)
Requested by secure CPU2. The
x Flash memory is mass erased.
Requested by CPU1. Mass erase
aborted (no erase started)
Erase aborted (no erase started)
WRPERR
Yes
RM0453 Rev 2
CPU1 CPU2
bus error bus error
No
No
Yes
N/A
No
No N/A
(2)
No
RM0453
Illegal
access
event
No
No
No
(1)
Yes
No