Table of Contents
Advertisement
Reset and clock control (RCC)
7.4.22
RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR)
Address offset: 0x068
Reset value: 0x0000 1007
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
CRC
Res.
Res.
Res.
SMEN
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during CPU1 CSleep mode.
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during CPU1 CSleep mode.
Bit 1 DMA2SMEN: DMA2 clock enable during CPU1 CSleep mode
Bit 0 DMA1SMEN: DMA1 clock enable during CPU1 CSleep mode.
324/1454
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
rw
This bit is set and cleared by software.
0: CRC clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: CRC clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1
CStop mode.
This bit is set and cleared by software.
0: DMAMUX1 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: DMAMUX1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
This bit is set and cleared by software.
0: DMA2 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: DMA2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
This bit is set and cleared by software.
0: DMA1 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: DMA1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
RM0453
17
16
Res.
Res.
1
0
rw
rw
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL55JC and is the answer not in the manual?
Questions and answers