ST STM32WL55JC Reference Manual page 519

RM0453
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PIF45: pending bit on event input 45
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 PIF41: pending bit on event input 41
Bit 8 PIF40: pending bit on event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PIF34: pending bit on event input 34
Bits 1:0 Reserved, must be kept at reset value.
16.6.9 EXTI interrupt mask register (EXTI_CnIMR1)
Address offset: Block 1: 0x080
Address offset: Block 2: 0x0C0
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 IM[31:0]: wakeup with interrupt mask on event input x (x= 31 to 0)
16.6.10 EXTI event mask register (EXTI_CnEMR1)
Address offset: Block 1: 0x084
Address offset: Block 2: 0x0C4
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
EM15 EM14 EM13 EM12
rw rw rw rw
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
27 26 25
rw rw rw
11 10 9
rw rw rw
For each bit of this field:
0: Wakeup with interrupt request from line x is masked.
1: Wakeup with Interrupt request from line x is unmasked.
27 26 25
Res. Res. Res.
11 10 9
EM11 EM10 EM9
rw rw rw
Extended interrupts and event controller (EXTI)
24 23 22
IM[31:16]
rw rw rw
8 7 6
IM[15:0]
rw rw rw
24 23 22
Res. Res. EM22 EM21
rw
8 7 6
EM8 EM7 EM6 EM5
rw rw rw
RM0453 Rev 2
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
EM20 EM19 EM18
rw rw rw rw
5 4 3 2
EM4 EM3 EM2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
EM17 Res.
rw
1 0
EM1 EM0
rw rw
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