ST STM32WL55JC Reference Manual page 134

Embedded Flash memory (FLASH)
Bit 31 LOCK: FLASH_CR lock
Bit 30 OPTLOCK: Options lock
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 OBL_LAUNCH: forces the option byte loading
Bit 26 RDERRIE: PCROP read error interrupt enable
Bit 25 ERRIE: error interrupt enable
Bit 24 EOPIE: end of operation interrupt enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 FSTPG: fast programming
Bit 17 OPTSTRT: options modification start
Bit 16 STRT: start
Bits 15:10 Reserved, must be kept at reset value.
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This bit can only be set by software. When set, the FLASH_CR register is locked. This bit is
cleared by hardware after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
This bit can only be set by software. When set, all bits concerning user option in FLASH_CR
and so option page are locked. This bit is cleared by hardware after detecting the option
unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for
OPTLOCK bit.
In case of an unsuccessful option unlock operation, this bit remains set until the next reset.
When set to 1, this bit forces the option byte reloading. This bit is cleared only when the
option byte loading is complete. It cannot be written if OPTLOCK is set.
0: Option byte loading completed
1: Option byte loading requested
This bit enables the interrupt generation when the RDERR bit in FLASH_SR is set to 1.
0: PCROP read error interrupt disabled
1: PCROP read error interrupt enabled
This bit enables the interrupt generation when the OPERR bit in FLASH_SR is set to 1.
0: OPERR error interrupt disabled
1: OPERR error interrupt enabled
This bit enables the interrupt generation when the EOP bit in FLASH_SR is set to 1.
0: EOP Interrupt disabled
1: EOP Interrupt enabled
0: Fast programming disabled
1: Fast programming enabled
When set, this bit triggers an options programming operation. When RDP level is regressed
from level 1 to level 0, this bit also launches a Flash memory, SRAM1 and SRAM2 erase.
This bit is set only by software and cleared when BSY is cleared in FLASH_SR.
When set, this bit triggers an erase operation. If MER and PER are reset and STRT is set, an
unpredictable behavior may occur without generating any error flag. This condition is
forbidden.
This bit is set only by software and cleared when BSY is cleared in FLASH_SR.
When the system is secure (ESE = 1) starting operations by the CPU1, involving secure
Flash pages are rejected and a bus error is generated.
RM0453 Rev 2
RM0453