Table 203. Lptim Register Map And Reset Values - ST STM32WL55JC Reference Manual

RM0453
30 Independent watchdog (IWDG)
30.1 Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to
984.
30.2 IWDG main features
•
Free-running downcounter
•
Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
•
Conditional reset
–
–
30.3 IWDG functional description
30.3.1 IWDG block diagram
Figure 270
V
CORE
Prescaler register
LSI
(32 kHz)
V voltage domain
DD
1. The register interface is located in the V
voltage domain, still functional in Stop and Standby mode.
Reset (if watchdog activated) when the downcounter value becomes lower than
0x000
Reset (if watchdog activated) if the downcounter is reloaded outside the window
shows the functional blocks of the independent watchdog module.
Figure 270. Independent watchdog block diagram
Status register
IWDG_PR IWDG_SR
8-bit
prescaler
Reload register
IWDG_RLR
12-bit reload value
12-bit downcounter
voltage domain. The watchdog function is located in the V
CORE
RM0453 Rev 2
Independent watchdog (IWDG)
Section 31 on page
Key register
IWDG_KR
IWDG reset
MS34442V1
DD
975/1454
983