ST STM32WL55JC Reference Manual page 887

RM0453
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Bits 31:0 CCR2[31:0]: Capture/Compare 2 value
26.4.18 TIM2 capture/compare register 3 (TIM2_CCR3)
Address offset: 0x3C
Reset value: 0x0000 0000
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Bits 31:0 CCR3[31:0]: Capture/Compare value
26.4.19 TIM2 capture/compare register 4 (TIM2_CCR4)
Address offset: 0x40
Reset value: 0x0000 0000
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If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.
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If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3). The
TIMx_CCR3 register is read-only and cannot be programmed.
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CCR2[31:16]
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CCR2[15:0]
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CCR3[31:16]
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CCR3[15:0]
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RM0453 Rev 2
General-purpose timer (TIM2)
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1 0
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