ST STM32WL55JC Reference Manual page 980

Independent watchdog (IWDG)
30.4.3 IWDG reload register (IWDG_RLR)
Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 RL[11:0]: Watchdog counter reload value
Note: Reading this register returns the reload value from the V
980/1454
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw
These bits are write access protected see
software to define the value to be loaded in the watchdog counter each time the value
0xAAAA is written in the
down from this value. The timeout period is a function of this value and the clock prescaler.
Refer to the datasheet for the timeout information.
The RVU bit in the IWDG status register (IWDG_SR)
reload value.
may not be up to date/valid if a write operation to this register is ongoing on it. For this
reason the value read from this register is valid only when the RVU bit in the
status register (IWDG_SR)
24 23 22
Res. Res. Res.
8 7 6
RL[11:0]
rw rw rw
Register access
IWDG key register (IWDG_KR). The watchdog counter counts
is reset.
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
protection. They are written by
must be reset to be able to change the
voltage domain. This value
DD
RM0453
17 16
Res. Res.
1 0
rw rw
IWDG