ST STM32WL55JC Reference Manual page 598

Digital-to-analog converter (DAC)
XOR
X
The LFSR value, that may be masked partially or totally by means of the MAMP1[3:0] bits in
the DAC_CR register, is added up to the DAC_DHR1 contents without overflow and this
value is then transferred into the DAC_DOR1 register.
If LFSR is 0x0000, a '1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVE1[1:0] bits.
Figure 90. DAC conversion (SW trigger enabled) with LFSR wave generation
dac_pclk
DHR
DOR
SWTRIG
Note: The DAC trigger must be enabled for noise generation by setting the TEN1 bit in the
DAC_CR register.
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Figure 89. DAC LFSR register calculation algorithm
12
11 10 9
0x00
6
X
8 7 6 5
12
NOR
0xAAA
RM0453 Rev 2
4
X X
4 3 2 1
0xD55
RM0453
0
X
0
ai14713c
MS45320V1