ST STM32WL55JC Reference Manual page 689

RM0453
Bits 31:0 DOUT[31:0]: Output data word
This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon
the computation completion (CCF set), virtually reads a complete 128-bit block of output data from
the AES peripheral. Before reaching the output buffer, the data produced by the AES core are
handled by the data swap block according to the DATATYPE[1:0] bitfield.
Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0].
The data signification of the output data block depends on the AES operating mode:
- Mode 1 (encryption): ciphertext
- Mode 2 (key derivation): the bitfield is not used
- Mode 3 (decryption): plaintext
The data swap operation is described in
page 678.
23.7.5 AES key register 0 (AES_KEYR0)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
w w w
15 14 13
w w w
Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0]
This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on
the operating mode:
- In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption
key.
- In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before
being used for decryption.
The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES
peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly
loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set).
Refer to
23.7.6 AES key register 1 (AES_KEYR1)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
w w w
15 14 13
w w w
28 27 26 25
w w w w
12 11 10 9
w w w w
Section 23.4.14: AES key registers on page 680
28 27 26 25
w w w w
12 11 10 9
w w w w
Section 23.4.13: AES data registers and data swapping on
24 23 22
KEY[31:16]
w w w
8 7 6
KEY[15:0]
w w w
for more details.
24 23 22
KEY[63:48]
w w w
8 7 6
KEY[47:32]
w w w
RM0453 Rev 2
AES hardware accelerator (AES)
21 20 19 18
w w w w
5 4 3 2
w w w w
21 20 19 18
w w w w
5 4 3 2
w w w w
17 16
w w
1 0
w w
17 16
w w
1 0
w w
689/1454
695