Table 91. Exti Pin Overview; Table 92. Evg Pin Overview; Figure 54. Exti Block Diagram - ST STM32WL55JC Reference Manual

Extended interrupts and event controller (EXTI)
EXTI
Acronym
o
n
14 EXTI[14]
15 EXTI[15]
16 PVD
17 RTC_ALARM
18 SSRU
TAMP,
19 RTC_STAMP,
LSE_CSS
20 RTC_WKUP
21 COMP1
22 COMP2
23 I2C1 wakeup
24 I2C2 wakeup
25 I2C3 wakeup
26 USART1
27 USART2
28 LPUART1
29 LPTIM1 wakeup
30 LPTIM2 wakeup
31 LPTIM3 wakeup
32 Reserved
33 Reserved
34 PVM[3]
35 Reserved
36 IPCC CPU1
37 IPCC CPU2
38 HSEM interrupt 0
39 HSEM interrupt 1
40 C2SEV
41 C1SEV
42 Flash
HSE32 CSS
43
interrupt
44 Radio IRQs
508/1454
Table 93. Wakeup interrupts (continued)
Description
EXTI line 14 from SYSCFG
EXTI line 15 from SYSCFG
PVD line
RTC alarms A and B interrupt
RTC SSR underflow interrupt
TAMP tamper interrupt
RTC timestamp interrupt
RCC LSECSS interrupt
RTC wakeup interrupt
COMP1 line
COMP2 line
I2C1 wakeup
I2C2 wakeup
I2C3 wakeup
USART1 wakeup
USART2 wakeup
LPUART1 wakeup
LPtimer 1 wakeup
LPtimer 2 wakeup
LPtimer 3 wakeup
-
-
PVM[3] line
-
IPCC CPU1 RX occupied and TX free
interrupts
IPCC CPU2 RX occupied and TX free
interrupts
Semaphore interrupt 0 with CPU1
Semaphore interrupt 1 with CPU2
CPU2 SEV line
CPU1 SEV line
Flash ECC and global interrupts
RCC HSE32 CSS interrupt
Radio IRQs interrupts
RM0453 Rev 2
EXTI type Event
Configurable Yes
Configurable Yes
Configurable No
Direct Yes
Direct Yes
Direct Yes
Direct Yes
Configurable Yes
Configurable Yes
Direct No
Direct No
Direct No
Direct No
Direct No
Direct No
Direct No
Direct No
Direct No
Direct No
Direct No
Configurable No
Direct No
Direct No
Direct No
Direct No
Direct No
Configurable Yes
Configurable Yes
Direct No
Direct No
Direct No
RM0453
Wakeup
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2
-
-
CPU1 and CPU2
-
(1)
CPU1
(2)
CPU2
(1)
CPU1
(2)
CPU2
(3)
CPU1
(4)
CPU2
CPU1 and CPU2
CPU1 and CPU2
CPU1 and CPU2