Watchdog Clock; True Rng Clock; Clock-Out Capability - ST STM32WL55JC Reference Manual

Reset and clock control (RCC)
Bit 18 PPRE2F: PCLK2 prescaler flag (APB2)
Bit 17 PPRE1F: PCLK1 prescaler flag (APB1)
Bit 16 HPREF: HCLK1 prescaler flag (CPU1, AHB1, and AHB2)
Bit 15 STOPWUCK: Wakeup from Stop and CSS backup clock selection
Note: Warning: STOPWUCK must not be modified when the HSE32 CSS is enabled by
Bit 14 Reserved, must be kept at reset value.
Bits 13:11 PPRE2[2:0]: PCLK2 high-speed prescaler (APB2)
Bits 10:8 PPRE1[2:0]: PCLK1 low-speed prescaler (APB1)
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This bit is set and reset by hardware to acknowledge PCLK2 prescaler programming. It is
reset when a new prescaler value is programmed in PPRE2 and set when the programmed
value is actually applied.
0: PCLK2 prescaler value not yet applied
1: PCLK2 prescaler value applied
This bit is set and reset by hardware to acknowledge PCLK1 prescaler programming. It is
reset when a new prescaler value is programmed in PPRE1 and set when the programmed
value is actually applied.
0: PCLK1 prescaler value not yet applied
1: PCLK1 prescaler value applied
This bit is set and reset by hardware to acknowledge HCLK1 prescaler programming. It is
reset when a new prescaler value is programmed in HPRE and set when the programmed
value is actually applied.
0: HCLK1 prescaler value not yet applied
1: HCLK1 prescaler value applied
This bit is set and cleared by software to select the system clock used when exiting Stop
mode. The selected clock is also used as emergency clock for the CSS on HSE32.
0: MSI oscillator selected as wakeup from stop clock and CSS backup clock.
1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock
CSSON in the RCC_CR register and the system clock is HSE32 (SWS = 10) or a
switch on HSE32 is requested (SW = 10).
These bits are set and cleared by software to control the division factor of the PCLK2 clock
(APB2). The PPRE2F flag can be checked to know if the programmed PPRE2 prescaler
value is applied.
0xx: HCLK1 not divided
100: HCLK1 divided by 2
101: HCLK1 divided by 4
110: HCLK1 divided by 8
111: HCLK1 divided by 16
These bits are set and cleared by software to control the division factor of the PCLK1 clock
(APB1). The PPRE1F flag can be checked to know if the programmed PPRE1 prescaler
value is applied.
0xx: HCLK1 not divided
100: HCLK1 divided by 2
101: HCLK1 divided by 4
110: HCLK1 divided by 8
111: HCLK1 divided by 16
RM0453 Rev 2
RM0453