ST STM32WL55JC Reference Manual page 785

RM0453
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 MMS2[3:0]: Master mode selection 2
These bits allow the information to be sent to ADC for synchronization (TRGO2) to be
selected. The combination is as follows:
0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If
0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is
0010: Update - the update event is selected as trigger output (TRGO2). For instance, a
0011: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to
0100: Compare - OC1REFC signal is used as trigger output (TRGO2)
0101: Compare - OC2REFC signal is used as trigger output (TRGO2)
0110: Compare - OC3REFC signal is used as trigger output (TRGO2)
0111: Compare - OC4REFC signal is used as trigger output (TRGO2)
1000: Compare - OC5REFC signal is used as trigger output (TRGO2)
1001: Compare - OC6REFC signal is used as trigger output (TRGO2)
1010: Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2
1011: Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2
1100: Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2
1101: Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on
1110: Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2
1111: Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
Bit 19 Reserved, must be kept at reset value.
Bit 18 OIS6: Output Idle state 6 (OC6 output)
Refer to OIS1 bit
Bit 17 Reserved, must be kept at reset value.
Bit 16 OIS5: Output Idle state 5 (OC5 output)
Refer to OIS1 bit
Bit 15 Reserved, must be kept at reset value.
Bit 14 OIS4: Output Idle state 4 (OC4 output)
Refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
Refer to OIS1N bit
the reset is generated by the trigger input (slave mode controller configured in reset
mode), the signal on TRGO2 is delayed compared to the actual reset.
useful to start several timers at the same time or to control a window in which a slave
timer is enabled. The Counter Enable signal is generated by a logic AND between the
CEN control bit and the trigger input when configured in Gated mode. When the
Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2,
except if the Master/Slave mode is selected (see the MSM bit description in
TIMx_SMCR register).
master timer can then be used as a prescaler for a slave timer.
be set (even if it was already high), as soon as a capture or compare match occurs
(TRGO2).
TRGO2
TRGO2
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
RM0453 Rev 2
Advanced-control timer (TIM1)
785/1454
822