ST STM32WL55JC Reference Manual page 39

RM0453
38.4.10 DP target identification register (DP_TARGETSELR) . . . . . . . . . . . . 1332
38.4.11 DP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
38.5 Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
38.5.1
38.5.2
38.5.3
38.5.4
38.5.5
38.5.6
38.5.7
38.6 Data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . . . . . . . . . . . 1342
38.6.1
38.6.2
38.6.3
38.6.4
38.6.5
38.6.6
38.6.7
38.6.8
38.6.9
38.6.10 DWT mask register x (DWT_MASKxR) . . . . . . . . . . . . . . . . . . . . . . . 1348
38.6.11 DWT function register x (DWT_FUNCTxR) . . . . . . . . . . . . . . . . . . . . 1348
38.6.12 DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . . . 1349
38.6.13 DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . . . 1350
38.6.14 DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . . . 1350
38.6.15 DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . . . 1351
38.6.16 DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . . . 1351
38.6.17 DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . . 1352
38.6.18 DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . . . 1352
38.6.19 DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . . 1353
38.6.20 DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . . 1353
38.6.21 DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 1353
38.7 Cross trigger interface (CTI) and cross trigger matrix (CTM) . . . . . . . . 1356
38.7.1
38.8 CPU1 ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
38.8.1
38.8.2
AP control/status word register (AP_CSWR) . . . . . . . . . . . . . . . . . . . 1338
AP transfer address register (AP_TAR) . . . . . . . . . . . . . . . . . . . . . . . 1339
AP data read/write register (AP_DRWR) . . . . . . . . . . . . . . . . . . . . . . 1339
AP banked data registers x (AP_BDxR) . . . . . . . . . . . . . . . . . . . . . . 1340
AP base address register (AP_BASER) . . . . . . . . . . . . . . . . . . . . . . 1340
AP identification register (AP_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
AP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
DWT control register (DWT_CTRLR) . . . . . . . . . . . . . . . . . . . . . . . . 1343
DWT cycle count register (DWT_CYCCNTR) . . . . . . . . . . . . . . . . . . 1345
DWT CPI count register (DWT_CPICNTR) . . . . . . . . . . . . . . . . . . . . 1345
DWT exception count register (DWT_EXCCNTR) . . . . . . . . . . . . . . . 1345
DWT sleep count register (DWT_SLPCNTR) . . . . . . . . . . . . . . . . . . 1346
DWT LSU count register (DWT_LSUCNTR) . . . . . . . . . . . . . . . . . . . 1346
DWT fold count register (DWT_FOLDCNTR) . . . . . . . . . . . . . . . . . . 1347
DWT program counter sample register (DWT_PCSR) . . . . . . . . . . . 1347
DWT comparator register x (DWT_COMPxR) . . . . . . . . . . . . . . . . . . 1347
CTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
CPU1 ROM memory type register (ROM_MEMTYPER) . . . . . . . . . . 1378
CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4) . 1379
RM0453 Rev 2
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