Flash Memory In Low-Power Mode For Code Execution From Ram; Sleep Mode; Table 15. Sleep-Now Entry And Exit - ST STM32F410 Reference Manual

RM0401
Section 5.3.8: RCC AHB1 peripheral clock enable register
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
4.3.4

Flash memory in low-power mode for code execution from RAM

For applications where the code is executed from RAM, the Flash memory can be put in two
possible low-power mode.
• Stop mode
•
Deep-power down mode
Putting the Flash memory in Deep-power down mode allows to achieve the best power
consumption. However the Flash memory wakeup time is the slowest (refer to the
Electrical characteristics section of the datasheet).
From Run mode, the Flash memory can be configured anytime by software to enter any of
these low-power mode.
From Sleep mode, setting the Flash memory low-power down mode must be done before
entering Sleep mode.
The Flash memory wakeup time has to be handled by software counter.
4.3.5

Sleep mode

Entering Sleep mode
The Sleep mode is entered according to
SLEEPDEEP bit in the Cortex
Refer to
Exiting Sleep mode
The Sleep mode is exited according to
Refer to
Sleep-now mode
Mode entry
®
Table 15 and Table 16
Table 15 and Table 16

Table 15. Sleep-now entry and exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex
On Return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex
Section : Entering low-power
-M4 with FPU System Control register is cleared.
for details on how to enter Sleep mode.
Section : Exiting low-power
for more details on how to exit Sleep mode.
Description
®
-M4 with FPU System Control register.
®
-M4 with FPU System Control register.
RM0401 Rev 3
Power controller (PWR)
(RCC_AHB1ENR)).
mode, when the
mode.
77/771
90