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1
6
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2 /
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o r
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p
7.5 CPU Clock and Peripheral Function Clock
The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the peripheral
functions.
7.5.1 CPU Clock
This is the operating clock for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
CM0 register and bits CM17 to CM16 in CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to 0 and
bits CM17 and CM16 to 00
After reset, the on-chip oscillator clock divided by 16 provides the CPU clock.
Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to 1 (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode).
7.5.2 Peripheral Function Clock(f
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fi
divided by i. The clock fi is used for Timer A, Timer B, SI/O3 and SI/O4 while fiSIO is used for UART0 to
UART2. Additionally, the f1 and f2 clocks are also used for dead time timer, Timer S, multi-master I
The f
clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/
AD
D converter.
The f
clock is derived from the main clock, PLL clock or on-chip oscillator clock devided by 1 (undi-
CAN0
vided), 2, 4, 8, or 16, and is used for the CAN module.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral
function clock turned off during wait mode), or when the MCU is in low power dissipation mode, the fi, fi
f
, and f
clocks are turned off. (Note 1)
AD
CAN0
The f
clock is produced from the sub clock, and is used for timers A and B. This clock can only be used
C32
when the sub clock is on.
Note 1: f
clock stops at "H" in CAN0 sleep mode.
CAN0
7.5.3 ClockOutput Function
The f
, f
, f
or f
1
8
32
and bits CM01 to CM00 in the CM0 register to select. Table 7.3 shows the function of the CLK
Table 7.3 The function of the CLK
PCLK5
CM01
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
(undivided).
2
are derived from the main clock, PLL clock, or on-chip oscillator clock
SIO
clock can be output from the CLK
C
pin
OUT
CM00
The function of the CLK
0
I/O port P9
1
f
C
0
f
8
1
f
32
0
f
1
1
Do not set
0
Do not set
1
Do not set
page 58
f o
4
5
8
, f
, f
, f
, f
, f
1
2
8
32
1SIO
pin. Use the PCLK5 bit in the PCLKR register
OUT
OUT
0
7. Clock Generation Circuit
, f
, f
, f
2SIO
8SIO
32SIO
pin
, f
, f
)
AD
C32
CAN0
2
C bus.
,
SIO
pin.
OUT
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