Supervisor Instruction Set - Freescale Semiconductor MCF52277 Reference Manual

Debug Module
Table 32-26. PST/DDATA Values for User-Mode Multiply-Accumulate Instructions (continued)
Instruction
move.l
move.l
msac.l
msac.l
msac.w
msac.w
32.7.2

Supervisor Instruction Set

The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown
below. The PST/DDATA specification for these opcodes is shown in
Table 32-27. PST/DDATA Specification for Supervisor-Mode Instructions
Instruction Operand Syntax
cpushl (Ax)
halt
move.l Ay,USP
move.l USP,Ax
move.w SR,Dx
move.w {Dy,#<data>},SR
movec.l Ry,Rc
rte
stldsr.w #imm
stop #<data>
wdebug.l <ea>y
The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into user
mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a
multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xFF)
display this status throughout the entire time the ColdFire processor is in the given mode.
32-48
Operand Syntax
MACSR,Rx
MASK,Rx
Ry,Rx,ACCx
Ry,Rx,<ea>y,Rw,ACCx
Ry,Rx,ACCx
Ry,Rx,<ea>y,Rw,ACCx
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0x3}
PST = 0x1
PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 0x3}, { PST = 0x B,
DD =source operand},
PST = 0x5, {[PST = 0x9AB], DD = target address}
PST = 0x1, {PST = 0xA, DD = destination operand, PST = 0x3}
PST = 0x1,
PST = 0xE
PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
MCF52277 Reference Manual, Rev. 1
PST/DDATA
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
Table
PST/DDATA
32-27.
Freescale Semiconductor