Freescale Semiconductor MCF52277 Reference Manual page 739

Last Byte
Transmitted
?
N
RXAK= 0
?
Y
End of
Y
ADDR Cycle
(Master RX)
?
N
Write Next
Byte to I2DR
Switch to
Rx Mode
Generate
Dummy Read
from I2DR STOP Signal
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TX TX/Rx RX
?
Y
Last
Byte to be
N
?
Read
N
2nd Last
Byte to be
Y
Read?
N
Generate
Set TXAK =1
STOP Signal
Read Data
from I2DR
And Store
Figure 31-14. Flow-Chart of Typical I
MCF52277 Reference Manual, Rev. 1
Clear
IIF
Y N
Master
Mode?
Clear IAL
N
IAAS=1
Y
Y
Address
Cycle
(Read)
Y
SRW=1
Set TX
Mode
Write Data
to I2DR
Set RX
Mode
Dummy Read
from I2DR
RTE
2
C Interrupt Routine
Y
Arbitration
Lost?
N
Y
IAAS=1
? ?
N
Data
Cycle
Tx/Rx
?
?
N (WRITE) TX
Y ACK from
Receiver
?
N
Read Data
Tx Next
from I2DR
Byte
and Store
Switch to
Rx Mode
Dummy Read
from I2DR
2
I C Interface
RX
31-15