Freescale Semiconductor MCF52277 Reference Manual page 730

2
I C Interface
2
31.2.4 I C Status Register (I2SR)
The I2SR contains bits that indicate transaction direction and status.
Address: 0xFC05_800C (I2SR)
7
R ICF
W
Reset: 1
Field
2
7 I C Data transferring bit. While one byte of data is transferred, ICF is cleared.
ICF 0 Transfer in progress
1 Transfer complete. Set by falling edge of ninth clock of a byte transfer.
2
6 I C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set
IAAS its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
2
5 I C bus busy bit. Indicates the status of the bus.
IBB 0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
2
4 I C arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero
IAL to it.)
• I2C_SDA sampled low when the master drives high during an address or data-transmit cycle.
• I2C_SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
3 Reserved, must be cleared.
2 Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent
SRW from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated,
2
and the I C module is a slave and has an address match.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
2
1 I C interrupt. Must be cleared by software by writing a 0 in the interrupt routine.
2
IIF 0 No I C interrupt pending
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following
occurs:
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
0 Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.
RXAK 0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.
31-6
6 5
IAAS IBB
0 0
Figure 31-5. I2SR Register
Table 31-5. I2SR Field Descriptions
MCF52277 Reference Manual, Rev. 1
4 3
0 SRW
IAL
0 0
Description
Access: User read/write
2 1
RXAK
IIF
0 0
Freescale Semiconductor
0
1