Freescale Semiconductor MCF52277 Reference Manual page 583

Address: 0xFC0B_C014 (SISRR)
31 30 29
R 0 0
W
Reset 0 0
15 14 13
R RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS
W
Reset 0 0
Field
31–19 Reserved, must be cleared.
18 AC97 command address register updated. This bit causes the command address updated interrupt when the
CMDAU SSI_IER[CMDAU] bit is set. This status bit is set each time there is a difference in the previous and current value
of the received command address. This bit is cleared upon reading the SSI_ACADD register.
0 No change in SSI_ACADD register
1 SSI_ACADD register updated with different value
17 AC97 command data register updated. This bit causes the command data updated interrupt when the
CMDU SSI_IER[CMDDU] bit is set. This status bit is set each time there is a difference in the previous and current value
of the received command data. This bit is cleared upon reading the SSI_ACDAT register.
0 No change in SSI_ACDAT register
1 SSI_ACDAT register updated with different value
16 AC97 receive tag updated. This status bit is set each time there is a difference in the previous and current value
RXT of the received tag. It causes the receive tag interrupt if the SSI_IER[RXT] bit is set. This bit is cleared upon
reading the SSI_ATAG register.
0 No change in SSI_ATAG register
1 SSI_ATAG register updated with different value
Freescale Semiconductor
28 27 26
0 0 0 0
0 0 0 0
12 11 10
1 1 0 0
Figure 25-15. SSI Interrupt Status Register (SSI_ISR)
Table 25-8. SSI_ISR Field Descriptions
MCF52277 Reference Manual, Rev. 1
25 24 23 22
0 0 0 0
0 0 0 0
9 8 7 6
RFS
0 0 0 0
Description
Synchronous Serial Interface (SSI)
Access: User read-only
21 20 19 18
0 0 0 CMDAU CMDDU RXT
0 0 0 0
5 4 3 2
TLS RLS RFF1 RFF0
0 0 0 0
17 16
0 0
1 0
TFE1 TFE0
1 1
25-15