Freescale Semiconductor MCF52277 Reference Manual page 778

Debug Module
Command/Result Formats:
15
Command
Result
Command Sequence:
WCREG
??? 'NOT READY'
Operand Data:
Result Data:
32.5.3.3.14 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the RDMREG command is CSR (DRc = 0x00). This read of the CSR clears CSR (FOF, TRG, HALT, and
BKPT) as well as the trigger status bits (CSR[BSTAT]) if a level-2 breakpoint is triggered or a level-1
breakpoint is triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
32-38
14 13 12 11 10
0x2
0x0
0x0
Figure 32-38.
WCREG
MS ADDR MS ADDR
'NOT READY'
Figure 32-39.
This instruction requires two longword operands. The first selects the register to
the operand data writes to; the second contains the data.
Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
MCF52277 Reference Manual, Rev. 1
9 8 7 6
0x8 0x8
0x0 0x0
Rc
D[31:16]
D[15:0]
Command/Result Formats
MS DATA
'NOT READY'
LS DATA
'NOT READY'
Command Sequence
WCREG
)
RDMREG
5 4 3 2 1
0x0
0x0
WRITE
XXX
CONTROL
'NOT READY'
REGISTER
NEXT CMD
'CMD COMPLETE'
XXX
BERR
NEXT CMD
'NOT READY'
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