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Power Management
8.3.4.16
LCD Controller
In wait and doze modes, the LCD controller continues operation and is capable of generating an interrupt
to wake-up the core from these modes. In stop mode, the LCD controller is disabled and cannot generate
an interrupt to wake-up the device.
8.3.4.17
FlexCAN
When enabled, the FlexCAN module is capable of generating interrupts and bringing the device out of a
low-power mode.
When setting stop mode in the FlexCAN (by setting the CANMCR[MDIS] bit), the FlexCAN checks for
the CAN bus to be idle or waits for the third bit of intermission and checks to see if it is recessive. When
this condition exists, the FlexCAN waits for all internal activity other than in the CAN bus interface to
complete and then the following occurs:
•
The FlexCAN shuts down its clocks, stopping most of the internal circuits, to achieve maximum
possible power saving.
•
The internal bus interface logic continues operation, enabling CPU to access the CANMCR
register.
•
The FlexCAN ignores its Rx input pin, and drives its Tx pins as recessive.
•
FlexCAN loses synchronization with the CAN bus, and the CANMCR[STOP_ACK, NOT_RDY]
bits are set.
Exiting stop mode is done in one of the following ways:
•
Reset the FlexCAN (by hard reset or by asserting the CANMCR[SOFT_RST] bit).
•
Clearing the CANMCR[MDIS] bit.
Recommendations for, and features of, FlexCAN's stop mode operation are as follows:
•
Upon stop mode entry, the FlexCAN tries to receive the frame that caused it to wake; it assumes
that the dominant bit detected is a start-of-frame bit. It does not arbitrate for the CAN bus then.
•
Before asserting stop mode, the CPU should disable all interrupts in the FlexCAN, otherwise it
may be interrupted while in stop mode upon a non-wake-up condition.
•
If stop mode is asserted while the FlexCAN is BUSOFF (see error and status register), then the
FlexCAN enters stop mode and stops counting the synchronization sequence; it continues this
count after stop mode is exited.
•
If halt mode is active at the time the MDIS bit is set, then the FlexCAN assumes that halt mode
should be exited; hence it tries to synchronize to the CAN bus (11 consecutive recessive bits), and
only then does it search for the correct conditions to stop.
•
Trying to stop the FlexCAN immediately after reset is allowed only after basic initialization has
been performed.
8-14
MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor
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