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Address: 0xFC04_801F (SLMASK)
7
R
0
W
Reset:
0
Field
7–4
Reserved, must be cleared.
3–0
Saved level mask. Defines the saved level mask. See the CLMASK field definition for more information on the
SLMASK
specific values.
15.2.9
Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63))
Each ICR register specifies the interrupt level (1–7) for the corresponding interrupt source. These registers
are cleared by reset and should be programmed with the appropriate levels before interrupts are enabled.
When multiple interrupt requests are programmed to the same level number, they are processed in a
descending request number order. As an example, if requests 63, 62, 2, and 1 are programmed to a common
level, request 63 is processed first, then request 62, then request 2, and finally request 1.
This definition allows software maximum flexibility in grouping interrupt request sources within any
given priority level. The priority level in the ICRs directly corresponds to the interrupt level supported by
the ColdFire processor.
Address: 0xFC04_8040–7F (ICR000–ICR063)
0xFC04_C040–7F (ICR100–ICR163)
7
R
0
W
Reset:
0
Field
7–3
Reserved, must be cleared.
2–0
Interrupt level. Indicates the interrupt level assigned to each interrupt input. A level of 0 effectively disables the
LEVEL
interrupt request, while a level 7 interrupt is given the highest priority.
If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgement of a level-n request forces the
controller to automatically mask all interrupt requests of level-n and lower.
Freescale Semiconductor
6
5
0
0
0
0
Figure 15-11. Saved Level Mask Register (SLMASK)
Table 15-13. SLMASK Field Descriptions
6
5
0
0
0
0
Figure 15-12. Interrupt Control Registers (ICR0n, ICR1n)
Table 15-14. ICRn Field Descriptions
MCF52277 Reference Manual, Rev. 1
4
3
0
0
1
Description
4
3
0
0
0
0
Description
Interrupt Controller Modules
Access: User read/write
2
1
0
SLMASK
1
1
1
Access: User read/write
2
1
0
LEVEL
0
0
0
15-11
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