Freescale Semiconductor MCF52277 Reference Manual page 419

20.5.3.4.2 Priming Receive Endpoints
Priming receives endpoints identical to priming of transmit endpoints from the point of view of the DCD.
The major difference in the operational model at the device controller is no data movement of the leading
packet data because the data is to be received from the host.
As part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like
the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints.
20.5.3.4.3 Interrupt/Bulk Endpoint Operation
The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT
transactions to bulk pipes handshake with a NAK unless the endpoint is primed. After the endpoint is
primed, data delivery commences.
A dTD is retired by the device controller when the packets described in the transfer descriptor are
completed. Each dTD describes N packets to transfer according to the USB variable length transfer
protocol. The formula below and
length of the packets sent/received by the USB vary according to the total number of bytes and maximum
packet length. See Section 20.5.2.1.1, "Endpoint Capabilities/Characteristics (Offset =
on the ZLT bit.
With zero-length termination (ZLT) cleared:
N = INT(number of bytes/max. packet length) + 1
With zero-length termination (ZLT) set:
N = MAXINT(number of bytes/max. packet length)
Table 20-52. Variable Length Transfer Protocol Example (ZLT=0)
Bytes
(dTD)
Table 20-53. Variable Length Transfer Protocol Example (ZLT=1)
Bytes
(dTD)
511
512
512
The MULT field in the dQH must be set to 00 for bulk, interrupt, and control
endpoints.
Freescale Semiconductor
Table 20-52
Max. Packet
Length (dQH)
511 256
512 256
512 512
Max. Packet
Length (dQH)
256
256
512
MCF52277 Reference Manual, Rev. 1
Universal Serial Bus Interface – On-The-Go Module
describe how the device controller computes the number and
N P1
2 256 255
3 256 256
2 512
N P1
2 256
2 256
1 512
NOTE
0x0)," for details
P2 P3
—
0
0 —
P2 P3
255 —
256 —
— —
20-61