Functional Description - Freescale Semiconductor MCF52277 Reference Manual

DMA Serial Peripheral Interface (DSPI)
Field
31–16 Reserved, must be cleared.
15–0 Receive data. Contains the received SPI data.
RXDATA
29.4

Functional Description

The DSPI supports full-duplex, synchronous serial communications between the MCU and external
peripheral devices. The DSPI supports up to 32 queued SPI transfers at once (16 transmit and 16 receive)
in the DSPI resident FIFOs, thereby eliminating CPU intervention between transfers.
The DSPI_CTARn registers hold clock and transfer attributes. The SPI configuration can select which
CTAR to use on a frame by frame basis by setting the DSPI_PUSHR[CTAS] field. See
"DSPI Clock and Transfer Attributes Registers 0–7
fields.
The 16-bit shift register in the master and the 16-bit shift register in the slave are linked by the SOUT and
SIN signals to form a distributed 32-bit register. When a data transfer operation is performed, data is
serially shifted a pre-determined number of bit positions. Because the registers are linked, data exchanged
between the master and the slave; the data that was in the master's shift register is now in the shift register
of the slave and vice versa. At the end of a transfer, the DSPI_SR[TCF] bit is set to indicate a completed
transfer. Figure 29-11
Baud Rate Generator
The DSPI has three peripheral chip select (DSPI_PCSn) signals that select which of the slaves to
communicate with.
Transfer protocols and timing properties are shared by the three DSPI configurations; these properties are
described independently of the configuration in
delay settings are described in section
See Section 29.4.7, "Power Saving
29.4.1 Start and Stop of DSPI Transfers
The DSPI has two operating states; stopped and running. The default state of the DSPI is stopped. In the
stopped state, no serial transfers are initiated in master mode and no transfers are responded to in slave
29-20
Table 29-11. DSPI_RXFRn Field Description
illustrates how master and slave data is exchanged.
DSPI Master
Shift Register
Figure 29-11. SPI Serial Protocol Overview
Section 29.4.3, "DSPI Baud Rate and Clock Delay Generation."
Features" for information on the power-saving features of the DSPI.
MCF52277 Reference Manual, Rev. 1
Description
(DSPI_CTARn)," for information on DSPI_CTARn
SIN SOUT
SOUT SIN
SCK SCK
PCSn SS
Section 29.4.4, "Transfer Formats."
Section 29.3.3,
DSPI Slave
Shift Register
The transfer rate and
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