Freescale Semiconductor MCF52277 Reference Manual page 116

Cache
Field
28 Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bits
CPDI [12:4] of the address is invalidated if CPDI is cleared. If CPDI is set, no operation is performed.
0 Enable invalidation
1 Disable invalidation
27 Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can
CFRZ be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given cache location
is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
26–25 Reserved, must be cleared.
24 Cache invalidate. The cache invalidate operation is not a function of the CENB state (this operation is independent
CINV of the cache being enabled or disabled). Setting this bit forces the cache to invalidate all, half, or none of the tag array
entries depending on the state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several
cycles of overhead plus 512 machine cycles to clear all tag array entries and 256 cycles to clear half of the tag array
entries, with a single cache entry cleared per machine cycle. The state of this bit is always read as a zero. After a
hardware reset, the cache must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 5-4 describes how to set the cache invalidate all bit.
23 Disable instruction caching. When set, this bit disables instruction caching. This bit, along with the CENB (cache
DISI enable) and DISD (disable data caching) bits, control the cache configuration. See the CENB definition for a detailed
description.
0 Enable instruction caching
1 Disable instruction caching
Table 5-3 describes cache configuration and
22 Disable data caching. When set, this bit disables data caching. This bit, along with the CENB (cache enable) and
DISD DISI (disable instruction caching) bits, control the cache configuration. See the CENB definition for a detailed
description.
0 Enable data caching
1 Disable data caching
Table 5-3 describes cache configuration and
21 CINV instruction cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared).
INVI For instruction or data cache configurations this bit is a don't-care. For the split cache configuration, this bit is part of
the control for the invalidate all operation. See the CINV definition for a detailed description
Table 5-4 describes how to set the cache invalidate all bit.
20 CINV data cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared). For
INVD instruction or data cache configurations this bit is a don't-care. For the split cache configuration, this bit is part of the
control for the invalidate all operation. See the CINV definition for a detailed description
Table 5-4 describes how to set the cache invalidate all bit.
19–11 Reserved, must be cleared.
10 Cache enable non-cacheable instruction bursting. Setting this bit enables the line-fill buffer to be loaded with burst
CEIB transfers under control of CLNF[1:0] for non-cacheable accesses. Non-cacheable accesses are never written into
the memory array. See
0 Disable burst fetches on non-cacheable accesses
1 Enable burst fetches on non-cacheable accesses
5-4
Table 5-2. CACR Field Descriptions (continued)
Table 5-4
Table 5-4
Table 5-7.
MCF52277 Reference Manual, Rev. 1
Description
describes how to set the cache invalidate all bit.
describes how to set the cache invalidate all bit.
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