Accumulator Registers (Acc0–3) - Freescale Semiconductor MCF52277 Reference Manual

Enhanced Multiply-Accumulate Unit (EMAC)
The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is:
if extension word, bit [5] = 1, the MASK bit, then
if <ea> = (An)
oa
if <ea> = (An)+
oa
An = (An + 4) & {0xFFFF, MASK}
if <ea> =-(An)
oa
An = (An - 4) & {0xFFFF, MASK}
if <ea> = (d16,An)
oa
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also
shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue
implementations.
BDM: 0x805 (MASK)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Field
31–16 Reserved, must be set.
15–0 Performs a simple AND with the operand address for MAC instructions.
MASK
4.2.3 Accumulator Registers (ACC0–3)
The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers
form the entire 48-bit result.
4-6
= An & {0xFFFF, MASK}
= An
= (An - 4) & {0xFFFF, MASK}
= (An + se_d16) & {0xFFFF0x, MASK}
Figure 4-3. Mask Register (MASK)
Table 4-4. MASK Field Descriptions
MCF52277 Reference Manual, Rev. 1
8
MASK
Description
Access: User read/write
BDM read/write
7 6 5 4 3 2 1 0
Freescale Semiconductor