Initialization/Application Information - Freescale Semiconductor MCF52277 Reference Manual

DMA Serial Peripheral Interface (DSPI)
29.5

Initialization/Application Information

29.5.1 How to Change Queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. This section presents an example of how to change queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag, DSPI_SR[EOQF] is set.
3. The setting of the EOQF flag disables serial transmission and serial reception of data, putting the
DSPI in the stopped state. The TXRXS bit is cleared to indicate the stopped state.
4. The eDMA continues to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the eDMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
DSPI_SR[RXCNT] bit or by checking the DSPI_SR[RFDF] bit after each read operation of the
DSPI_POPR register.
7. Modify DMA descriptor of TX and RX channels for new queues.
8. Flush TX FIFO by writing a 1 to the DSPI_MCR[CLR_TXF] bit; Flush RX FIFO by writing a 1
to the DSPI_MCR[CLR_RXF] bit.
9. Clear transfer count by setting the CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to the DSPI_TCR[SPI_TCNT] field.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
29.5.2 Switching Master and Slave Mode
When changing modes in the DSPI, follow the steps below to guarantee proper operation.
1. Halt the DSPI by setting DSPI_MCR[HALT].
2. Clear the transmit and receive FIFOs by writing a 1 to the CLR_TXF and CLR_RXF bits in
DSPI_MCR.
3. Set the appropriate mode in DSPI_MCR[MSTR] and enable the DSPI by clearing
DSPI_MCR[HALT].
29.5.3 Baud Rate Settings
Table 29-19 shows the baud rate generated based on the combination of the baud rate prescaler PBR and
the baud rate scaler BR in the DSPI_CTARn registers. The values calculated assume a 100 MHz system
frequency.
29-36
MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor