Lcdc Interrupt Enable Register (Lcd_Ier) - Freescale Semiconductor MCF52277 Reference Manual

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Field
2
Interrupt source. Determines if an interrupt flag is set during last data/first data of frame loading or on last data/first
INT_SYN
data of frame output to the LCD panel. Please refer to the below table for INTSYN/INTCON setting usage.
There is a latency between loading the last/first data of frame to output to LCD panel.
0 Interrupt flag is set on loading the last data/first data of frame from memory
1 Interrupt flag is set on output of the last data/first data of frame to LCD panel
1
Reserved, must be cleared.
0
Interrupt condition. Determines if an interrupt condition is set at the beginning or the end of frame condition. Refer
INT_CON
to table in the INT_SYN field description for INTSYN/INTCON setting usage.
0 Interrupt flag is set when the End of Frame (EOF) is reached
1 Interrupt flag is set when the Beginning of Frame (BOF) is reached

21.3.16 LCDC Interrupt Enable Register (LCD_IER)

The LCDC interrupt enable Register is used to enable the LCDC interrupt signal generated to the interrupt
controller. When the interrupt is masked, the LCDC does not generate the interrupt request, but its status
can be observed in the interrupt status register.
Address: 0xFC0A_C03C (LCD_IER)
31
30
29
R
0
0
W
Reset
0
0
15
14
13
R
0
0
W
Reset
0
0
Freescale Semiconductor
Table 21-18. LCD_ICR Field Descriptions (continued)
INTSYN INTCON
0
0
1
1
28
27
26
0
0
0
0
0
0
0
0
12
11
10
0
0
0
0
0
0
0
0
Figure 21-18. LCD Interrupt Endable Register (LCD_IER)
MCF52277 Reference Manual, Rev. 1
Description
Description
0
Interrupt flag is set on loading last data of
frame from memory.
1
Interrupt flag is set on loading first data of
frame from memory.
0
Interrupt flag is set on output of last data
of frame to LCD panel.
1
Interrupt flag is set on output of first data
of frame to LCD panel.
25
24
23
22
0
0
0
0
0
0
0
0
9
8
7
6
0
0
GW
GW
UDR
ERR
0
0
0
0
Liquid Crystal Display Controller (LCDC)
Access: User read/write
21
20
19
18
0
0
0
0
0
0
0
0
5
4
3
2
GW
GW
UDR
ERR
EOF
BOF
0
0
0
0
17
16
0
0
0
0
1
0
EOF
BOF
0
0
21-19

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