Freescale Semiconductor MCF52277 Reference Manual page 612

Synchronous Serial Interface (SSI)
(PSR), prescaler modulus (PM), and frame rate (DC) selects the ratio of SSI_MCLK to sampling clock,
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SSI_FS. In I S mode, the oversampling clock is available on this port if the SSI_CR[MCE] bit is set.
Figure 25-36 shows the relationship between the clocks and the dividers. The bit clock can be received
from an SSI clock port or generated from the internal clock (SSI_CLOCK) through a divider, as shown in
Figure 25-37.
Serial Bit Clock
25.4.2.1 SSI Clock and Frame Sync Generation
Data clock and frame sync signals can be generated internally or obtained from external sources. If
internally generated, the SSI clock generator derives bit clock and frame sync signals from the
SSI_CLOCK. The SSI clock generator consists of a selectable, fixed prescaler and a programmable
prescaler for bit rate clock generation. A programmable frame rate divider and a word length divider are
used for frame rate sync signal generation.
Figure 25-37 shows a block diagram of the clock generator for the transmit section. The serial bit clock
can be internal or external, depending on the transmit direction (SSI_TCR[TXDIR]) bit.
CDR[SSIDIV]
Internal core clock
(f )
sys (/3 to /62)
SSI_CLKIN
SSI_MCLK
SSI_BCLK
Figure 25-38 shows the frame sync generator block for the transmit section. When internally generated,
receive and transmit frame sync generate from the word clock and are defined by the frame rate divider
(DC) bits and the word length (WL) bits of the SSI_CCR.
25-44
Word Divider
(/8, /10, /12, /16,
/18, /20, /22, /24)
Figure 25-36. SSI Clocking
CCM
MISCCR[SSISRC]
Divider
1
SSI_CLOCK
0
TXDIR
MCE
TXDIR(1=output)
TXDIR(0=input)
Figure 25-37. SSI Transmit Clock Generator Block Diagram
MCF52277 Reference Manual, Rev. 1
Word clock
Frame Divider
(/1 to /32)
SSI_CCR[DIV2] SSI_CCR[PSR]
Divider Prescaler
(/1 or /2) (/1 or /8)
TXDIR(1=output)
Serial Bit Clock
Frame clock
SSI_CCR[PM]
Divider
(/1 to /256)
Divide by
Word Length
Word clock
Divider
SSI_CCR[WL]
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