Memory Map/Register Definition - Freescale Semiconductor MCF52277 Reference Manual

System Control Module (SCM)
12.2

Memory Map/Register Definition

The memory map for the SCM registers is shown in
Attempted accesses to reserved addresses result in a bus error, while attempted writes to read-only registers
are ignored and do not terminate with an error. Unless noted otherwise, writes to the programming model
must match the size of the register, e.g., an 8-bit register supports only 8-bit writes, etc. Attempted writes
of a different size than the register width produce a bus error and no change to the targeted register.
Address
0xFC00_0000 Master Privilege Register (MPR)
0xFC00_0020 Peripheral Access Control Register A (PACRA)
0xFC00_0024 Peripheral Access Control Register B (PACRB)
0xFC00_0028 Peripheral Access Control Register C (PACRC)
0xFC00_002C Peripheral Access Control Register D (PACRD)
0xFC00_0040 Peripheral Access Control Register E (PACRE)
0xFC00_0044 Peripheral Access Control Register F (PACRF)
0xFC00_0048 Peripheral Access Control Register G (PACRG)
0xFC00_0050 Peripheral Access Control Register I (PACRI)
0xFC04_0013 Wakeup Control Register (WCR)
0xFC04_0016 Core Watchdog Control Register (CWCR)
0xFC04_001B Core Watchdog Service Register (CWSR)
0xFC04_001F SCM Interrupt Status Register (SCMISR)
0xFC04_0024 Burst Configuration Register (BCR)
0xFC04_0070 Core Fault Address Register (CFADR)
0xFC04_0075 Core Fault Interrupt Enable Register (CFIER)
0xFC04_0076 Core Fault Location Register (CFLOC)
0xFC04_0077 Core Fault Attributes Register (CFATR)
0xFC04_007C Core Fault Data Register (CFDTR)
1
The WCR register is described in
12.2.1 Master Privilege Register (MPR)
The MPR specifies five 4-bit fields defining the access-privilege level associated with a bus master in the
device to the various peripherals listed in
12-2
Table 12-1. SCM Memory Map
Register
1
Chapter 8, "Power Management."
Table 12-4. The register provides one field per bus master.
MCF52277 Reference Manual, Rev. 1
Table 12-1.
Width
Access Reset Value
(bits)
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
8 R/W
16 R/W
8 R/W
8 R/W
32 R/W
32 R
8 R/W
8 R
8 R
32 R
Section/Page
0x7000_0007 12.2.1/12-2
0x5444_4444 12.2.2/12-3
0x4444_4444 12.2.2/12-3
0x4444_4444 12.2.2/12-3
0x4444_4444 12.2.2/12-3
0x4444_4444 12.2.2/12-3
0x4444_4444 12.2.2/12-3
0x4444_4444 12.2.2/12-3
0x4400_0000 12.2.2/12-3
0x00 8.2.1/8-2
0x0000 12.2.3/12-7
Undefined 12.2.4/12-8
0x00 12.2.5/12-8
0x0000_0000 12.2.6/12-9
0x0000_0000 12.2.7/12-10
0x00 12.2.8/12-10
Undefined 12.2.9/12-11
Undefined 12.2.10/12-11
Undefined 12.2.11/12-12
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