Initialization/Application Information - Freescale Semiconductor MCF52277 Reference Manual

SDRAM Controller (SDRAMC)
19.5.1.8 Self-Refresh (SREF) and Power Down (PDWN) Commands
The memory controller issues a PDWN or a SREF command if the SDCR[CKE] bit is cleared. If the
SDCR[REF_EN] bit is set when CKE is negated, the controller issues a SREF command; if the REF_EN
bit is cleared, the controller issues a PDWN command. The REF_EN bit may be changed in the same
register write that changes the CKE bit; the controller acts upon the new value of the REF_EN bit.
Like an auto-refresh command, the controller automatically issues a
command.
The memory reactivates from power-down or self-refresh mode by setting the CKE bit.
If a normal refresh interval elapses while the memory is in self-refresh mode, a PALL and REF performs
when the memory reactivates. If the memory is put into and brought out of self-refresh all within a
single-refresh interval, the next automatic refresh occurs on schedule.
In self-refresh mode, memory does not require an external clock. The SD_CLK can be stopped for
maximum power savings. If the memory controller clock is stopped, the refresh-interval timer must be
reset before the memory is reactivated (if periodic refresh is to be resumed). The refresh-interval timer
resets by clearing the REF_EN bit. This can be done at any time while the memory is in self-refresh mode,
before or after the memory controller clock is stopped/restarted, but not with the same control register
write that clears CKE; this would put the memory in power down mode. To restart periodic refresh when
the memory reactivates, the REF_EN bit must be reasserted; this can be done before the memory
reactivates or in the same control register write that sets CKE to exit self-refresh mode.
19.6

Initialization/Application Information

SDRAMs have a prescribed initialization sequence. The following section details the memory
initialization steps for DDR SDRAM. The sequence might change slightly from device-to-device. Refer
to the device datasheet as the most relevant reference.
1. After reset is deactivated, pause for the amount of time indicated in SDRAM specification. Usually
100μs or 200μs.
2. Configure pin multiplex control for shared SD_CS pins in pin multiplexing and control module.
3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module's
MSCR_SDRAM register.
4. Write the base address and mask registers (SDBAR0, SDBAR1, SDMR0, and SDMR1) to setup
the address space for each chip-select.
5. Program SDRAM configuration registers (SDCFG1 and SDCFG2) with correct delay and timing
values.
6. Issue a command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set.
PALL
The SDCR[REF and IREF] bits should remain cleared for this step.
7. Initialize the SDRAM's extended mode register to enable the DLL. See
Mode/Extended Mode Register Command (lmr, lemr),"
command.
19-26
MCF52277 Reference Manual, Rev. 1
command before the self-refresh
PALL
Section 19.5.1.6, "Load
for instructions on issuing a
Freescale Semiconductor
LEMR