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The SSI module typically transfers samples in a periodic manner. The SSI consists of independent
transmitter and receiver sections with shared clock generation and frame synchronization.
The pin multiplexing and control module must be configured to enable the
peripheral function of the appropriate pins (refer to ") prior to configuring
the SSI.
25.1.2
Features
The SSI includes the following features:
•
Synchronous transmit and receive sections with shared internal/external clocks and frame syncs,
operating in master or slave mode.
•
Normal mode operation using frame sync
•
Network mode operation allowing multiple devices to share the port with up to 32 time slots
•
Gated clock mode operation requiring no frame sync
•
Two sets of transmit and receive FIFOs. Each of the four FIFOs is 8x24 bits, which can be used in
network mode to provide two independent channels for transmission and reception
•
Programmable data interface modes such as I
•
Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
•
Program options for frame sync and clock generation
•
Programmable I
SSI_MCLK in I
•
AC97 support
•
Completely separate clock and frame sync selections. In the AC97 standard, the clock is taken from
an external source and frame sync is generated internally.
•
Programmable oversampling clock (SSI_MCLK) of the sampling frequency available as output in
master mode
•
Programmable internal clock divider
•
Transmit and receive time slot mask registers for reduced CPU overhead
•
SSI power-down feature
25.1.3
Modes of Operation
SSI has the following basic synchronous operating modes.
•
Normal mode
•
Network mode
•
Gated clock mode
These modes can be programmed via the SSI control registers.
some of the typical applications in which they can be used:
Freescale Semiconductor
2
S modes (master or slave). Oversampling clock available as output from
2
S master mode
MCF52277 Reference Manual, Rev. 1
NOTE
2
S, lsb, msb aligned
Table 25-1
Synchronous Serial Interface (SSI)
lists these operating modes and
25-3
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