Freescale Semiconductor MCF52277 Reference Manual page 753

DRc[4:0]: 0x07 (TDR)
31 30
R
W TRC L2EBL
Reset 0 0
15 14
R
W L2T L1T L1EBL
Reset 0 0
Field
31–30 Trigger Response Control. Determines how the processor responds to a completed trigger condition. The trigger
TRC response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
29 Enable Level 2 Breakpoint. Global enable for the breakpoint trigger.
L2EBL 0 Disables all level 2 breakpoints
1 Enables all level 2 breakpoint triggers
28–22 Enable Level 2 Data Breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on
L2ED the size and placement on the processor's local data bus. Clearing all ED bits disables data breakpoints.
21 Level 2 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a
L2DI trigger based on the occurrence of a data value other than the DBR contents.
0 No inversion
1 Invert data breakpoint comparators.
Freescale Semiconductor
29 28 27 26
0 0 0 0
13 12 11 10
0 0 0 0
Figure 32-6. Trigger Definition Register (TDR)
Table 32-9. TDR Field Descriptions
TDR Bit
28 Data longword. Entire processor's local data bus.
27 Lower data word.
26 Upper data word.
25 Lower lower data byte. Low-order byte of the low-order word.
24 Lower middle data byte. High-order byte of the low-order word.
23 Upper middle data byte. Low-order byte of the high-order word.
22 Upper upper data byte. High-order byte of the high-order word.
MCF52277 Reference Manual, Rev. 1
Second Level Trigger
25 24 23 22
L2ED
0 0 0 0
First Level Trigger
9 8 7 6
L1ED
0 0 0 0
Description
Description
Access: Supervisor write-only
21 20 19 18
L2DI L2EA
0 0 0 0
5 4 3 2
L1DI L1EA
0 0 0 0
Debug Module
BDM write-only
17 16
L2EPC L2PCI
0 0
1 0
L1EPC L1PCI
0 0
32-13